(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and is directed to a method of forming small (sub half-micrometer) contacts to devices on semiconductor substrates for Ultra Large Scale Integration (ULSI) circuits. More specifically, the method achieves higher packing density of storage cells on dynamic random access memory (DRAM) chips.
(2) Description of the Prior Art
In recent years, the integrated circuit density on the semiconductor substrate have dramatically increased. This increase in density has resulted from down scaling of the individual devices built in and on the substrate and the interconnecting patterned electrical conducting layers that are used to wire up the devices. Future requirements for even greater increases in packing density is putting additional demand on the semiconductor technologies, such as improved resolution in the photolithography and plasma etching techniques.
One processing area limiting the packing density is the fabrication of reliable small contacts to the semiconductor substrate between the closely spaced discrete devices. And more particularly, it is important to make good electrical contact to the source/drain areas of the field effect transistors (FETS) on integrated circuits chips such as the dynamic random access memory (DRAM), static random access memory (SRAM) and the like. One method of making reliable contacts to the substrate having closely spaced interconnecting wiring is described by J. K. Kim, U.S. Pat. No. 5,358,903, however, the method does not address the concern of making contacts adjacent to devices, such as are required for source/drain areas of FETs.
It is common practice in the semiconductor industry to use self-aligned contacts to the source/drain areas of FETs to achieve tighter design ground rules, and thereby achieving a high packing density on the chip. For example, referring now to FIG. 1, a schematic cross sectional view of a partially completed FET is shown having a patterned photoresist mask 40 for etching a conventional self-aligned contact opening 6 to one of the two source/drain areas 8 of an FET, such as on DRAM chips. FIG. 1 shows a portion of the silicon substrate 10 having an active device area surrounded by a field oxide (FOX) areas 12. A patterned polysilicon layer 16 is used to form word lines 16 on the DRAM circuit with the portion over the active device area serving as the gate electrode 16' of the FET. An insulating layers 20 and insulating side wall spacers 22, composed of, for example, silicon oxide, are formed, respectively, over and on the side of the gate electrode 16' and also on the word lines 16. After forming doped source/drain regions 24, for example, by ion implantation, an insulating layer 26, such as silicon oxide, is deposited on the substrate to insulate the source/drain contacts 24. A patterned photoresist mask 40 and etching is then used to etch the self-aligned contact openings 6, as shown in FIG. 1. When the overlapping contact opening 6 is etched in the insulating layer 26 and the thin gate oxide 11 to the source/drain area 24, the insulating layer 20 and the side wall spacers 22 protect the gate electrode from shorting to the source/drain 24 when an electrical contact (not shown in FIG. 1) is made to the source/drain areas 24 .
Unfortunately, as the device packing density on future integrated circuits continues to increase, such as on the array of storage cells of future 64 megabit, 256 megabit and higher megabit DRAM chips, the lateral dimensions of the spacing between word lines and gate electrodes must further decrease. This leads to a problem in forming the self aligned contacts, as is depicted for a high density chip in FIG. 2. For example, referring now to FIG. 2, when the spacing are reduced to about 0.4 micrometers or less between the word lines 16 and also between gate electrodes 16' over device areas, the insulating layer 26 conformally coats, and thereby fills the spaces between the lines. This forms a planar or almost planar surface on the insulating layer 26. If a conventional self-aligning contact opening 6, is etched using the photoresist mask 40 and anisotropic etching, then the insulating layer 20 and sidewall spacers 22 are unintentionally removed over portions of the gate electrode 16' and word line 16. This occurs since the insulating layer 26 is substantially thinner over the word line than over the source/drain areas 24. This results in electrical shorts between the source/drain area 24 and gate electrode 16' at the points A and B, as depicted in FIG. 2. when the electrical contacts (not shown) are made to the source/drain areas 24.
Therefore, there is still a strong need in the semiconductor industry for forming very small electrical contacts for ULSI circuits that have closely spaced patterned conducting layers in order to avoid the shorting problem. There is also a strong need in the semiconductor industry for making these small contacts using conventional optical photolithographic techniques so as to avoid the added cost required in using more advanced shorter wavelength lithographies, such as X-ray and electron beams.